Masaki Yonekura and Hiroki Is…
I/Q Mismatch Compensation ΔΣ Modulator Using Ternary Capacitor Rotation Technique,
A 1.6 Gs/S 3.17 mW 6-B Passive Pipelined Binary-Search ADC with Memory Effect Canceller and Reference Voltage Calibration,
Koki Tanaka, Ryo Saito, and H…
バイナリサーチとフラッシュ動作の動的切替を用いたパワースケーラブルADC
田中公貴，吉岡健太郎，斎藤涼，石黒仁揮，
「バイナリサーチ…
1-W 3.3?16.3-V Boosting Wireless Power Transfer Circuits With Vector Summing Power Controller ,
K. Tomita, R. Shinoda, T. Kuro…
High-Frequency Precise Characterization of Intrinsic FinFET,
H. Sakai, S. Ouchi, T. Matsuka…
A 0.5V 1.1 MS/sec 6.3 fJ/Conversion-Step SAR-ADC With Tri-Level Comparator in 40 nm CMOS,
A. Shikata, S. Ouchi, T. Kurod…
A 0.5-V 5.2-fJ/Conversion-Step Full Asynchronous SAR ADC With Leakage Power Reduction Down to 650 pW by Boosted Self-Power Gating in 40-nm CMOS,
R. Sekimoto, A. Shikata, K. Yo…
A 0.0058mm2 7.0 ENOB 24MS/s 17fJ/conv. Threshold Configuring SAR ADC with Source Voltage Shifting and Interpolation Technique,
K. Yoshioka, A. Shikata, R. Se…
Large Electron Addition Energy above 250 meV in the Silicon Quantum Dot in a Single Electron Transistor
Large Electron Addition Energy…
47% Power Reduction and 91% Area Reduction in Inductive-Coupling Programmable Bus for NAND Flash Memory Stacking,
M. Saito, Y. Yoshida, N. Miura…