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S. Moriwaki, Y. Yamamoto, S. Miyano, Y. Hiraku, I.Hayashi, K. Yoshioka, A. Shikata, H. Ishikuro, M. Ahn, Y. Okuma, X. Zhang,Y. Ryu, K. Ishida, M. Takamiya, T. Kuroda, H. Shinohara, and T. Sakurai,
"0.5V Image Processor with 563 GOPS/W SIMD and 32bit CPU Using High Voltage Clock Distribution (HVCD) and Adaptive Frequency Scaling (AFS) with 40nm CMOS,"
IEEE Symposium on VLSI Circuits, Dig. Tech. Papers, pp. C36-C37, June.14, 2013.
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