Akira Shikata, Ryota Sekimoto, Tadahiro Kuroda, and Hiroki Ishikuro, "A 0.5V 1.1MS/sec 6.3fJ/conversion-step SAR-ADC with Tri-Level Comparator in 40nm CMOS," VLSIシンポジウム報告会、7月28日、東京工業大学
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