A. Shikata, R. Sekimoto, T. Kuroda and H. Ishikuro, "A 0.5V 1.1MS/sec 6.3fJ/conversion-step SAR-ADC with Tri-Level Comparator in 40nm CMOS," at 2011 Symposium on VLSI Circuits, June 15-17, Kyoto, Japan.
Similar posts
Kaoru Yamashita received the Outstanding Student Paper Award at CICC2023
May 12, 2023A Dual-Mode 2:1 Switched Capacitor Converter with >65% Efficiency over 1000x Load Current Range and One Clock Cycle Transient Response
April 2, 2023Yi Tan, Hiroki Ishikuro, “A Dual-Mode 2:1 Switched Capacitor Converter with >65% Efficiency over 1000x Load Current Range and One Clock Cycle Transient Response” presented at 2022 29th IEEE International Conference on Electronics, Circuits and Systems (ICECS), Glasgow, United Kingdom, 24-26 October 2022
In Situ Monitoring Technique of Self-Heating in Bulk MOSFETs at Cryogenic Temperatures using Subthreshold Current
April 2, 2023Masayuki Ichikawa, Takahisa Tanaka, Ken Uchida, Tomohisa Miyao, Munehiro Tada, and Hiroki Ishikuro, “In Situ Monitoring Technique of Self-Heating in Bulk MOSFETs at Cryogenic Temperatures using Subthreshold Current” presented at 2022 IEEE Latin American Electron Devices Conference (LAEDC), Cancun, Mexico, 04-06 July 2022
No Comments Yet