M. Saito, Y. Yoshida, N. Miura, H. Ishikuro, and T. Kuroda, "47% Power Reduction and 91% Area Reduction in Inductive-Coupling Programmable Bus for NAND Flash Memory Stacking," IEEE Transactions on Circuits and Systems I, Vol. 57 , No. 9
pp.2269 ? 2278, Sept. 2010.
Similar posts
Peter Toth received the Jan Van Vessem Award for Outstanding EWAA Paper at ISSCC2026
March 6, 2026A 4.2–373 K Functional 800-MS/s 12-b Buffer-Then-Amplify Charge-Pump-Based Pipelined TI-SAR ADC With Integrated Active-Hold Technique
January 12, 2026K. Yamashita, K. Yoshioka, C. Ziegler, V. Issakov and H. Ishikuro, “A 4.2–373 K Functional 800-MS/s 12-b Buffer-Then-Amplify Charge-Pump-Based Pipelined TI-SAR ADC With Integrated Active-Hold Technique,” in IEEE Journal of Solid-State Circuits, 2025.
A 4.6–400 K Functional Ringamp-Based 250 MS/s 12 b Pipelined ADC With PVT-Robust Unity-Gain-Frequency-Aware Bias Calibration
January 12, 2026K. Yamashita, B. Hershberg, K. Yoshioka and H. Ishikuro, “A 4.6–400 K Functional Ringamp-Based 250 MS/s 12 b Pipelined ADC With PVT-Robust Unity-Gain-Frequency-Aware Bias Calibration,” in IEEE Journal of Solid-State Circuits, vol. 59, no. 3, pp. 740-752, March 2024

No Comments Yet