Effects of interface traps in silicon-quantum-dots-based memory structures ; X. L. Yuan, Y. Shi, S. L. Gu, J. M. Zhu, Y. D. Zheng, K. Saito, H. Ishikuro, and T. Hiramoto ; Physica E ; ; ; V.8/No.2/P.189-193 ; 2000/08?
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