Akira Shikata, Ryota Sekimoto,…
A 0.5V 1.1MS/sec 6.3fJ/conversion-step SAR-ADC with Tri-Level Comparator in 40nm CMOS,
0.5V動作の高速近接無線通信用送受信機の設計
松原、林、ジョハリ、熊木、小平、黒田、石黒、「0.5V動作の…
0.5Vアナログ回路設計の課題
石黒、「0.5Vアナログ回路設計の課題」電気学会研究会、7月…
A 40nm 50S/S – 8MS/S Ultra Low-Voltage SAR ADC with Timing Optimized Asynchronous Clock Generator
Ryota Sekimoto, Akira Shikata,…
A Power Scalable SAR-ADC in 0.18um-CMOS with 0.5V Nano-Watt Operation
Ryota Sekimoto, Akira Shikata,…
A 0.5V 1.1MS/sec 6.3fJ/conversion-step SAR-ADC with Tri-Level Comparator in 40nm CMOS,
A. Shikata, R. Sekimoto, T. Ku…
A 12Gb/s non-contact interface with coupled Transmission list01s,
T.Takeya, L.Nan, S.Nakano, N….
0.5V動作6-bitスケーラブル位相補間器
熊木、ジョハリ、松原、・林、石黒、「0.5V動作6-bitス…
0.5 V multi-phase digital controlled oscillator with smooth phase transition circuit,
A.H.Johari, S.Kumaki, T.Matsub…
A 0.5V 65nm-CMOS single phase clocked bootstrapped switch with rise time accelerator,
A.Shikata, R.Sekimoto, and H….