A. Shikata, R. Sekimoto, T. Kuroda and H. Ishikuro, "A 0.5V 1.1MS/sec 6.3fJ/conversion-step SAR-ADC with Tri-Level Comparator in 40nm CMOS," at 2011 Symposium on VLSI Circuits, June 15-17, Kyoto, Japan.
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