浦野雄貴、尹 元柱、小平 薫、徐 照男、黒田忠広、石黒仁揮、…
TDC一体型DLLを用いた高速ロック・低消費電力完全デジタルCDR回路
A 40nm CMOS Full Asynchronous Nano-Watt SAR ADC with 98% Leakage Power Reduction by Boosted Self Power Gating,
Ryota Sekimoto, Akira Shikata,…
タイミング最適化非同期クロック生成器を搭載した40nm超低電圧SAR ADC
関本竜太、志方明、吉岡健太郎、黒田忠広、石黒仁揮、「タイミン…
多相発振器による適応パルス幅制御を用いた低電圧・高速磁界結合通信機
浦野雄貴、松原岳志、林勇、アブル・ハサン・ジョハリ、小平薫、…
1/f Noise Characteristic in Independent-Double-Gate-FinFET
Hideo Sakai, Shin-ichi O’uchi,…
An 8bit .8V MS/s 2bit/step SAR ADC with Wide Range Threshold Configuring Comparator
Kentaro Yoshioka, Akira Shikat…
Voltage-Boosting Wireless Power Delivery System With Fast Load Tracker by ΔΣ-Modulated Sub-Harmonic Resonant Switching,
Ryota Shinoda, Kazutoshi Tomit…
A 0.7V 4.1mW 850Mbps/ch Inductive-Coupling Transceiver with Adaptive Pulse Width Controller in 65nm CMOS,
Takeshi Matsubara, Isamu Hayas…
A 0.5-V 5.2-fJ/Conversion-Step Full Asynchronous SAR ADC With Leakage Power Reduction Down to 650 pW by Boosted Self-Power Gating in 40-nm CMOS,
R. Sekimoto, A. Shikata, K. Yo…
A 0.0058mm2 7.0 ENOB 24MS/s 17fJ/conv. Threshold Configuring SAR ADC with Source Voltage Shifting and Interpolation Technique,
K. Yoshioka, A. Shikata, R. Se…