K. Yoshioka, A. Shikata, R. Sekimoto, T. Kuroda, and H. Ishikuro,
"A 0.0058mm2 7.0 ENOB 24MS/s 17fJ/conv. Threshold Configuring SAR ADC with Source Voltage Shifting and Interpolation Technique,"
IEEE Symposium on VLSI Circuits, Dig. Tech. Papers, pp. C266-C267, June.14, 2013.
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