K. Yoshioka, A. Shikata, R. Sekimoto, T. Kuroda, and H. Ishikuro,
"A 0.0058mm2 7.0 ENOB 24MS/s 17fJ/conv. Threshold Configuring SAR ADC with Source Voltage Shifting and Interpolation Technique,"
IEEE Symposium on VLSI Circuits, Dig. Tech. Papers, pp. C266-C267, June.14, 2013.
同様の投稿
13.3 A Cryo-BiCMOS Controller for 9Be+-Trapped-Ion-Based Quantum Computers
1月 12, 2026Peter Toth, Paul Shine Eugine, Yerzhan Kudabay, Kaoru Yamashita, Sebastian Halama, Hiroki Ishikuro, Christian […]
A 4.6-373K Functional 800MS/s 12b Buffer-then-Amplify Charge-Pump-Based Pipelined TI-SAR ADC with Integrated-Active-Hold Technique
1月 12, 2026K. Yamashita, K. Yoshioka, C. Ziegler, V. Issakov and H. Ishikuro, “A 4.6-373K Functional 800MS/s 12b Bu […]
A 4.6–400 K Functional Ringamp-Based 250 MS/s 12 b Pipelined ADC With PVT-Robust Unity-Gain-Frequency-Aware Bias Calibration
1月 12, 2026K. Yamashita, B. Hershberg, K. Yoshioka and H. Ishikuro, “A 4.6–400 K Functional Ringamp-Based 250 MS/s 12 b P […]
コメントはまだありません