慶応義塾大学理工学部　石黒研究室

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研究業績

学術論文誌 2012年

  • K. Tomita, R. Shinoda, T. Kuroda, and H. Ishikuro“1-W 3.3?16.3-V Boosting Wireless Power Transfer Circuits With Vector Summing Power Controller ,” IEEE Journal of Solid-State Circuits, Vol.47 , No. 11, pp.2576 - 2585, Nov., 2012.
  • H. Sakai, S. Ouchi, T. Matsukawa, K. Kasuga, K. Endo, Y. Liu, J. Tsukada, Y. Ishikawa, T. Nakagawa, T. Sekigawa, H. Koike, K.Sakamoto, M. Masahara, H. Ishikuro “High-Frequency Precise Characterization of Intrinsic FinFET,” IEEE Transactions on Electronics, Vol. E95-C , No. 4, pp. 752 - 760, Apl., 2012.
  • A. Shikata, S. Ouchi, T. Kuroda, and H. Ishikuro“A 0.5V 1.1 MS/sec 6.3 fJ/Conversion-Step SAR-ADC With Tri-Level Comparator in 40 nm CMOS,” IEEE Journal of Solid-State Circuits, Vol.47 , No. 4, pp.1022 - 1030, Apr., 2012.
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2010年

  • H.Ishikuro, T.Kuroda, “Wireless proximity interfaces with a pulse-based inductive coupling technique,” IEEE Communications Magazine, vol. 48, no. 10, pp.192-199, Oct. 2010.
  • M. Saito, Y. Yoshida, N. Miura, H. Ishikuro, and T. Kuroda, “47% Power Reduction and 91% Area Reduction in Inductive-Coupling Programmable Bus for NAND Flash Memory Stacking,” IEEE Transactions on Circuits and Systems I, Vol. 57 , No. 9
    pp.2269 ? 2278, Sept. 2010.
  • K.Niitsu, Y. Kohama, Y. Sugimori, K. Kasuga, K. Osada, N. Irie, H. Ishikuro, and T. Kuroda, “Modeling and Experimental Verification of Misalignment Tolerance in Inductive-Coupling Inter-Chip Link for Low-Power 3-D System Integration,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol.18 , No. 8, pp. 1238 - 1243, Aug., 2010.
  • M. Saito, Y. Sugimori, Y. Kohama, Y. Yoshida, N. Miura, H. Ishikuro, T. Sakurai, and T. Kuroda, “2 Gb/s 15 pJ/b/chip Inductive-Coupling Programmable Bus for NAND Flash Memory Stacking,” IEEE Journal of Solid-State Circuits, Vol.45 , No. 1, pp.134 - 141, Jan., 2010.
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2009年

  • V.V.Kulkarni, M.Muqsith, N. Niitsu, H. Ishikuro, and T. Kuroda, ”A 750 Mb/s, 12 pJ/b, 6-to-10 GHz CMOS IR-UWB Transmitter With Embedded On-Chip Antenna,” IEEE Journal of Solid-State Circuits, ?Vol. 44 , No. 2, pp.394 ? 403, Feb., 2009.
  • N. Miura, Y. Kohama, Y. Sugimori, H. Ishikuro, T. Sakurai, and T. Kuroda, “A High-Speed Inductive-Coupling Link With Burst Transmission,” IEEE Journal of Solid-State Circuits, Vol. 44 , No. 3 , pp.947 - 955, March, 2009.
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2008年

  • N. Miura, H. Ishikuro, K.Niitsu, T. Sakurai, and T.Kuroda, “A 0.14 pJ/b Inductive-Coupling Transceiver With Digitally-Controlled Precise Pulse Shaping,” IEEE Journal of Solid-State Circuits, Vol. 43 , No. 1, pp. 285 ? 291, Jan. 2008.
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2007年

  • K.Ishida, A.Tamtrakarn, H.Ishikuro, M.Takamiya, and T. Sakurai,　“An Outside-Rail Opamp Design Relaxing Low-Voltage Constraint on Future Scaled Transistors,” IEICE Trans. Electron., vol. E90-C No.4, pp.786-792
  • K. Niitsu, N. Miura, M. Inoue, Y. Nakagawa, M. Tago, M. Mizuno, H. Ishikuro, and T. Kuroda, “60% Power Reduction in Inductive-Coupling Inter-Chip Link by Current-Sensing Technique,” Japanese Journal of Applied Physics, Vol. 46, No. 4B, pp. 2215-2219
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2005年以前

  • A 2.4-GHz Temperature compensated CMOS LC-VCO for Low Frequency Drift Low-Power Direct-Modulation GFSK Transmitter ; T. Tanzawa, H. Shibayama, R. Terauchi, K. Hisano, H. Ishikuro, S. Kousai, H.Majima, H. Kobayashi, T. Takayama, K. Agawa, M. Koizumi, and F. Hatori ; IEICE Trans. Electron ; 電子情報通信学会 ; ; V.E88-C4/No.4 ; 2005/04?
  • A Full-CMOS Single Chip Bluetooth LSI with 1.5MHz-IF Receiver and Direct Modulation Transmitter ; F. Hatori, H. Ishikuro, M. Hamada, K. Agawa, S. Kousai, H. Kobayashi, and D.M.Nguyen ; IEICE Trans. Electron. ; 電子情報通信学会 ; ; V.E87-C/No.4 ; 2004/04?
  • Large Electron Addition Energy above 250 meV in the Silicon Quantum Dot in a Single Electron Transistor ; M. Saitoh, N. Takahashi, H. Ishikuro, and T. Hiramoto ; Japanese Journal of Applied Physics ; ; ; V.40/No.3B/P.2010 - 2012 ; 2001/03?
  • Experimental Evidence for Quantum Mechanical Narrow Channel Effect in Ultra-Narrow MOSFETs ; H. Majima, H. Ishikuro, and T. Hiramoto ; IEEE Electron Devices Letters ; ; ; V.21/No.8/P.396 - 398 ; 2000/08 ?
  • Effects of interface traps in silicon-quantum-dots-based memory structures ; X. L. Yuan, Y. Shi, S. L. Gu, J. M. Zhu, Y. D. Zheng, K. Saito, H. Ishikuro, and T. Hiramoto ; Physica E ; ; ; V.8/No.2/P.189-193 ; 2000/08?
  • Impact of the Device Scaling on the Low-Frequency Noise in n-MOSFETs ; H. M. Bu, Y. Shi, X. L. Yuan, Y. D. Zheng, S. H. Gu, H. Majima, H. Ishikuro, and T. Hiramoto ; Applied Physics A ; ; ; V.A71/No.2/P.133 - 136 ; 2000/06?
  • Random telegraph signals and low-frequency noise in n-metal-oxide-semiconductor field-effect transistors with ultranarrow channels ; H. M. Bu, Y. Shi, X. L. Yuan, J. Wu, S. L. Gu, and Y. D. Zheng, H. Majima, H. Ishikuro, and T. Hiramoto ; Applied Physics Letters ; ; ; V.76/No.22/P.3259 - 3261 ; 2000/05?
  • Control of Coulomb blockade oscillations in silicon single electron transistor using silicon nano-crystal floating gates ; Nobuyoshi Takahashi, Hiroki Ishikuro, and Toshiro Hiramoto ; Applied Physics Letters ; ; ; V.76/No.2/P.209 - 211 ; 2000/01?
  • Quantum Energy and Charging Energy in Point Contact MOSFETs acting as Single Electron Transistors ; Toshiro Hiramoto and Hiroki Ishikuro ; Superlattices and Microstructures ; ; ; V.24/No.1-2/P.263 - 267 ; 1999?
  • Characteristic Distributions of Narrow Channel Metal-Oxide-Semiconductor Field-Effect-Transistor Memories with Silicon Nanocrystal Floating Gates ; Eiji Nagata, Nobuyoshi Takahashi, Yuri Yasuda, Takashi Inukai, Hiroki Ishikuro, and Toshiro Hiramoto ; Japanese Journal of Applied Physics ; ; ; V.38/No.12B/P.7230 - 7232 ; 1999/12?
  • Highly Integrated Single Electron Devices and Giga-bit Lithography ; Toshiro Hiramoto, H. Ishikuro, and H. Majima ; Journal of Photopolymer Science and Technology ; ; ; V.12/No.3/P.417 - 422 ; 1999/06?
  • Coulomb Blockade in VLSI-Compatible Multiple-Dot and Single-Dot MOSFETs ; Toshiro Hiramoto and Hiroki Ishikuro ; International Journal of Electronics ; ; ; V.86/No.5/P.591 - 603 ; 1999/05?
  • Measurement of Energetic and Lateral Distribution of Interface State Density in FD SOI MOSFETs ; Tran Ngoc Duyet, Hiroki Ishikuro, Yi Shi, Takuya Saraya, Makoto Takamiya, and Toshiro Hiramoto ; Japanese Journal of Applied Physics ; ; ; V.38/No.4B/P.2496 - 2500 ; 1999/04?
  • Characteristics of Narrow Channel MOSFET Memory Based on Silicon Nanocrystals ; Yi Shi, Kenichi Saito, Hiroki Ishikuro, and Toshiro Hiramoto ; Japanese Journal of Applied Physics ; ; ; V.38/No.4B/P.2453 - 2456 ; 1999/04?
  • On the origin of tunneling barriers in silicon single electron and single hole transistors ; H. Ishikuro and T. Hiramoto ; Applied Physics Letters ; ; ; V.74/No.8/P.1126 - 1128 ; 1999/02?
  • Effects of Interface Traps on Charge Retention Characteristics in Silicon-Quantum-Dot-Based Metal-Oxide-Semiconductor Diodes ; Yi Shi, Kenichi Saito, Hiroki Ishikuro, and Toshiro Hiramoto ; Japanese Journal of Applied Physics ; ; ; V.38/No.1B/P.425 - 428 ; 1999/01?
  • Fabrication of Nano-Scale Point Contact Metal-Oxide-Semiconductor Field-Effect-Transistors Using Micrometer-Scale Design Rule ; Hiroki Ishikuro and Toshiro Hiramoto ; Japanese Journal of Applied Physics ; ; ; V.38/No.1B/P.396-398 ; 1999/01?
  • Effects of traps on charge storage characteristics in metal-oxide-semiconductor memory structures based on silicon nanocrystals ; Y. Shi, K. Saito, H. Ishikuro, and T. Hiramoto ; Journal of Applied Physics ; ; ; V.84/No.4/P.2358-2360 ; 1998/08?
  • Suppression of Geometric Component of Charge Pumping Current in Thin Film SOI MOSFET ; N. Duyet, H. Ishikuro, M. Takamiya, T. Saraya, and T. Hiramoto ; Japanese Journal of Applied Physics ; ; ; V.37/No.7B/P.L855 - L858 ; 1998/07?
  • Hopping Transport in Multiple-Dot Silicon Single Electron MOSFET, Solid State Electronics ; H. Ishikuro and T. Hiramoto ; Solid State Electronics ; ; ; V.42/No.7-8/P.1425 - 1428 ; 1998/07?
  • Fabrication of Gate-All Around MOSFET by Silicon Anisotropic Etching Technique ; T. Mukaiyama, K. Saito, H. Ishikuro, M. Takamiya, T. Saraya, and T. Hiramoto ; Solid State Electronics ; ; ; V.42/No.7-8/P.1623 - 1626 ; 1998/06?
  • Quantum mechanical effects in the silicon quantum dot in a single-electron-transistor ; Hiroki Ishikuro and Toshiro Hiramoto ; Applied Physics Letters ; ; ; V.71/No.25/P.3691 - 3693 ; 1997/12?
  • Room Temperature Coulomb Blockade and Low Temperature Hopping Transport in a Multiple-Dot-Channel MOSFET ; T. Hiramoto, H. Ishikuro, T. Fujii, G. Hashiguchi, and T. Ikoma ; Japanese Journal of Applied Physics ; ; ; V.36/No.6B/P.4139 - 4142 ; 1997/06?
  • Characterization of Precisely Width-Controlled Si Quantum Wires Fabricated on SOI Substrates ; T. Hiramoto, H. Ishikuro, T. Fujii, T. Saraya, G. Hashiguchi, and T. Ikoma ; Physics B ; ; ; V.227/P.95 - 97 ; 1996?
  • Fabirication of Si Nano-Structures for Single Electron Device Applications by Anisotropic Etching ; T. Hiramoto, H. Ishikuro, K. Saito, T. Fujii, T. Saraya, G. Hashiguchi, and T. Ikoma ; Japanese Journal of Applied Physics ; ; ; V.35/No.12B/P.6664 - 6667 ; 1996/12?
  • Coulomb Blockade Oscillations at Room Temperature in a Si Quantum Wire Metal-Oxide-Semiconductor Field-Effect-Transistor Fabricated by Anisotropic Etching on a Silicon-on-Insulator Substrate ; H. Ishikuro, T. Fujii, T. Saraya, G. Hashiguchi, T. Hiramoto, and T. Ikoma ; Applied Physics Letters ; ; ; V.68/No.25/P.3585 - 3587 ; 1996/06?
  • Extremely Large Amplitude Random Telegraph Signals in a Very Narrow Split-Gate MOSFET at Low Temperatures ; H. Ishikuro, T. Saraya, T. Hiramoto, and T. Ikoma ; Japanese Journal of Applied Physics ; ; ; V.35/No.2B/P.858 - 860 ; 1996/02?
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