R. Sekimoto, A. Shikata, K. Yoshioka, T. Kuroda, H. Ishikuro,"A 0.5-V 5.2-fJ/Conversion-Step Full Asynchronous SAR ADC With Leakage Power Reduction Down to 650 pW by Boosted Self-Power Gating in 40-nm CMOS," IEEE Journal of Solid-State Circuits, Vol. 48, Issue 11, pp.2628-2636, Nov. 2013.
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