K.Niitsu, Y. Kohama, Y. Sugimori, K. Kasuga, K. Osada, N. Irie, H. Ishikuro, and T. Kuroda, "Modeling and Experimental Verification of Misalignment Tolerance in Inductive-Coupling Inter-Chip Link for Low-Power 3-D System Integration," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol.18 , No. 8, pp. 1238 – 1243, Aug., 2010.
同様の投稿
A Cryo-BiCMOS Controller for Quantum Computers based on Trapped Beryllium Ions
1月 12, 2026Peter Toth, Paul Shine Eugine, Yerzhan Kudabay, Kaoru Yamashita, Sebastian Halama, Judi Parvizinejad, Marco Bo […]
A 4.2–373 K Functional 800-MS/s 12-b Buffer-Then-Amplify Charge-Pump-Based Pipelined TI-SAR ADC With Integrated Active-Hold Technique
1月 12, 2026K. Yamashita, K. Yoshioka, C. Ziegler, V. Issakov and H. Ishikuro, “A 4.2–373 K Functional 800-MS/s 12-b […]
A 4.6–400 K Functional Ringamp-Based 250 MS/s 12 b Pipelined ADC With PVT-Robust Unity-Gain-Frequency-Aware Bias Calibration
1月 12, 2026K. Yamashita, B. Hershberg, K. Yoshioka and H. Ishikuro, “A 4.6–400 K Functional Ringamp-Based 250 MS/s 12 b P […]

コメントはまだありません